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Accemic introduces hidICE as a next generation trace approach

Zero wait state real-time emulation

Unique debug solution for higher CPU clock rates

Your key to real-time runtime verification and runtime reflection
No reserved pins for trace port necessary
No bond-out-chips required
Full AND continuous AND real-time trace
Unlimited support of complex breakpoint conditions
Debugging on difficult-to-access target hardware
Minimal chip core area for emulation control
One hidICE system supports different microcontroller families
Cost reduction and faster time-to-market


S4D 2010

The following papers will be presented by Accemic and its academic partners (Dresden University of Technology, University of Luebeck) at the "System, Software, SoC and Silicon Debug S4D Conference" Sept 15th-16th, 2010 Southampton, UK:

  • Rico Backasch, Christian Hochberger, Martin Leucker, Alexander Weiss "A GENERIC HARDWARE ARCHITECTURE FOR RUNTIME VERIFICATION"
  • Alexander Weiss, Rico Backasch, Christian Hochberger "AN OBSERVER BASED SYSTEM FOR CAPTURING FULL AND REAL-TIME TRACES FROM MULTI-CORE SOCS"


Multicore SPARC V8 (LEON3) hidICE demonstration system

Accemic provides a new 32 bit SPARC V8 based demonstration system for the hidICE technology.

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Accemic Announces Version 2.6 of Accemic MDE

The new Accemic MDE version 2.6 is now available. In addition to the already know features, version 2.6 now also supports Fujitsu 16LX MB90F880 series.

For details click here.
A demo version is available here.

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First hidICE patent granted by the European Patent Office

Accemic proudly announces that Accemic has been granted the patent EP 1 720 100 B1 concerning the hidICE technology and entitled "Method and apparatus for emulating a programmable unit" by the European Patent Office.




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